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Sourcecode Batteriemanagementsystem
pmic.h
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1 
43 /*
44  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45  */
46 #ifndef PMIC_H
47 #define PMIC_H
48 
49 #include <compiler.h>
50 //#include <ccp.h>
51 
52 #include <avr/interrupt.h>
53 
54 typedef uint8_t irqflags_t;
55 
56 static inline irqflags_t cpu_irq_save(void)
57 {
58  irqflags_t flags = SREG;
59  cli();
60  return flags;
61 }
62 
63 static inline void cpu_irq_restore(irqflags_t flags)
64 {
65  barrier();
66  SREG = flags;
67 }
68 
69 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
70 {
71  // flags ist SREG
72  return flags & CPU_I_bm;
73 }
74 
96 enum pmic_level {
97  PMIC_LVL_LOW = PMIC_LOLVLEN_bm,
98  PMIC_LVL_MEDIUM = PMIC_MEDLVLEN_bm,
99  PMIC_LVL_HIGH = PMIC_HILVLEN_bm,
100 
104  PMIC_LVL_NMI = PMIC_NMIEX_bp,
105 };
106 
112 };
113 
119 };
120 
127 static inline void pmic_init(void)
128 {
129  PMIC.CTRL = PMIC_LVL_LOW | PMIC_LVL_MEDIUM |
131 }
132 
138 static inline void pmic_enable_level(enum pmic_level level)
139 {
140  Assert((level & PMIC_LVL_NMI));
141 
142  PMIC.CTRL |= level;
143 }
144 
150 static inline void pmic_disable_level(enum pmic_level level)
151 {
152  Assert((level & PMIC_LVL_NMI));
153 
154  PMIC.CTRL &= ~level;
155 }
156 
164 static inline bool pmic_level_is_enabled(enum pmic_level level)
165 {
166  Assert((level & PMIC_LVL_NMI));
167 
168  return PMIC.CTRL & level;
169 }
170 
176 static inline enum pmic_level pmic_get_enabled_levels(void)
177 {
178  return (enum pmic_level)(PMIC.CTRL & (PMIC_LVL_LOW | PMIC_LVL_MEDIUM
179  | PMIC_LVL_HIGH));
180 }
181 
189 static inline bool pmic_level_is_executing(enum pmic_level level)
190 {
191  return PMIC.STATUS & level;
192 }
193 
202 static inline void pmic_set_scheduling(enum pmic_schedule schedule)
203 {
204  Assert(schedule < PMIC_NR_OF_SCHEDULES);
205 
206  switch (schedule) {
208  PMIC.CTRL &= ~PMIC_RREN_bm;
209  PMIC.INTPRI = 0;
210  break;
211 
213  PMIC.CTRL |= PMIC_RREN_bm;
214  break;
215 
216  default:
217  break;
218  };
219 }
220 
226 static inline void pmic_set_vector_location(enum pmic_vector vector)
227 {
228  uint8_t ctrl = PMIC.CTRL;
229 
230  Assert(vector < PMIC_NR_OF_VECTORS);
231 
232  switch (vector) {
234  ctrl &= ~PMIC_IVSEL_bm;
235  break;
236 
237  case PMIC_VEC_BOOT:
238  ctrl |= PMIC_IVSEL_bm;
239  break;
240 
241  default:
242  break;
243  }
244 
245  CCP = CCP_IOREG_gc;
246  PMIC.CTRL = ctrl;
247 }
248 
250 
251 
252 #endif /* PMIC_H */
static enum pmic_level pmic_get_enabled_levels(void)
Get currently enabled level(s)
Definition: pmic.h:176
pmic_schedule
Interrupt scheduling schemes.
Definition: pmic.h:115
static void pmic_init(void)
Initialize the PMIC.
Definition: pmic.h:127
Commonly used includes, types and macros.
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:46
static void pmic_set_vector_location(enum pmic_vector vector)
Set location of interrupt vectors.
Definition: pmic.h:226
Number of interrupt scheduling schemes.
Definition: pmic.h:118
static bool pmic_level_is_enabled(enum pmic_level level)
Check if specified interrupt level(s) is enabled.
Definition: pmic.h:164
Default, fixed priority scheduling.
Definition: pmic.h:116
Round-robin scheduling.
Definition: pmic.h:117
static void pmic_set_scheduling(enum pmic_schedule schedule)
Set interrupt scheduling for low-level interrupts.
Definition: pmic.h:202
Application section.
Definition: pmic.h:109
Medium-level interrupts.
Definition: pmic.h:98
pmic_level
Interrupt level bitmasks.
Definition: pmic.h:96
static void pmic_disable_level(enum pmic_level level)
Disable interrupts with specified level(s).
Definition: pmic.h:150
#define barrier()
Memory barrier.
Definition: compiler.h:36
Low-level interrupts.
Definition: pmic.h:97
static void pmic_enable_level(enum pmic_level level)
Enable interrupts with specified level(s).
Definition: pmic.h:138
Non-maskable interrupts.
Definition: pmic.h:104
High-level interrupts.
Definition: pmic.h:99
static bool pmic_level_is_executing(enum pmic_level level)
Check if an interrupt level(s) is currently executing.
Definition: pmic.h:189
pmic_vector
Interrupt vector locations.
Definition: pmic.h:108
Boot section.
Definition: pmic.h:110
Number of interrupt vector locations.
Definition: pmic.h:111