73 #ifndef TWI_MASTER_DRIVER_H 74 #define TWI_MASTER_DRIVER_H 78 #include <util/delay.h> 82 #define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5) 85 #define TWIM_STATUS_READY 0 86 #define TWIM_STATUS_BUSY 1 91 TWIM_RESULT_UNKNOWN = (0x00 << 0), TWIM_RESULT_OK = (0x01 << 0), TWIM_RESULT_BUFFER_OVERFLOW = (0x02 << 0), TWIM_RESULT_ARBITRATION_LOST = (0x03 << 0), TWIM_RESULT_BUS_ERROR = (0x04 << 0), TWIM_RESULT_NACK_RECEIVED = (0x05 << 0), TWIM_RESULT_FAIL = (0x06 << 0),
95 #define TWIM_WRITE_BUFFER_SIZE 8 96 #define TWIM_READ_BUFFER_SIZE 16 register8_t writeData[TWIM_WRITE_BUFFER_SIZE]
void TWI_MasterArbitrationLostBusErrorHandler(TWI_Master_t *twi)
TWI master arbitration lost and bus error interrupt handler.
TWI_MASTER_BUSSTATE_t TWI_MasterState(TWI_Master_t *twi)
Returns the TWI bus state.
bool TWI_MasterWriteRead(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite, uint8_t bytesToRead)
TWI write and/or read transaction.
void TWI_MasterReadHandler(TWI_Master_t *twi)
TWI master read interrupt handler.
register8_t readData[TWIM_READ_BUFFER_SIZE]
void TWI_MasterTransactionFinished(TWI_Master_t *twi, uint8_t result)
TWI transaction finished handler.
enum TWIM_RESULT_enum TWIM_RESULT_t
void TWI_MasterInit(TWI_Master_t *twi, TWI_t *module, TWI_MASTER_INTLVL_t intLevel, uint8_t baudRateRegisterSetting)
Initialise the TWI module.
bool TWI_MasterRead(TWI_Master_t *twi, uint8_t address, uint8_t bytesToRead)
TWI read transaction.
struct TWI_Master TWI_Master_t
TWI master driver struct.
void TWI_MasterInterruptHandler(TWI_Master_t *twi)
Common TWI master interrupt service routine.
bool TWI_MasterWrite(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite)
TWI write transaction.
void TWI_MasterWriteHandler(TWI_Master_t *twi)
TWI master write interrupt handler.
TWI master driver struct.
bool TWI_MasterReady(TWI_Master_t *twi)
Returns true if transaction is ready.
#define TWIM_WRITE_BUFFER_SIZE