1 

15 #include <stdio.h>

16 #include <stddef.h>

17 #include <avr/pgmspace.h>

18 

22 void Config32MHzClock ( void )

23 {

24  unsigned char tmp;

25 

26  //Security Signature to modify clock

27  CCP = CCP_IOREG_gc;

28 

29  // Initialise clock source to be 32MHz internal oscillator (no PLL)

30  OSC.CTRL = OSC_RC32MEN_bm;

31 

32  // enable internal 32MHz oscillator

33  while ( !(OSC.STATUS & OSC_RC32MRDY_bm) )

34  ; // wait for oscillator ready

35  CCP = CCP_IOREG_gc; //Security Signature to modify clock

36  CLK.CTRL = 0x01; //select sysclock 32MHz osc

37 

38  // get USBRCOSC

39  NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc;

40  tmp = pgm_read_byte( offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC) );

41 

42  // Clean up NVM Command register.

43  NVM_CMD = NVM_CMD_NO_OPERATION_gc;

44 

45  // enable DFLL for 32MHz osz and trim to 48MHz sync with USB start of frame

46  OSC.DFLLCTRL = OSC_RC32MCREF_USBSOF_gc;

47  DFLLRC32M.CALB = tmp;

48  DFLLRC32M.COMP1 = 0x1B; //Xmega AU manual, 4.17.19

49  DFLLRC32M.COMP2 = 0xB7;

50  DFLLRC32M.CTRL = DFLL_ENABLE_bm;

51 

52  // enable 32 MHZ osz (trimmed to 48MHZ for usb)

53  CCP = CCP_IOREG_gc; //Security Signature to modify clock

54  OSC.CTRL = OSC_RC32MEN_bm | OSC_RC2MEN_bm; // enable internal 32MHz oscillator

55 

56  while ( !(OSC.STATUS & OSC_RC32MRDY_bm) )

57  ; // wait for oscillator ready

58 

59  OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | 16; // 2MHz * 16 = 32MHz

60 

61  CCP = CCP_IOREG_gc;

62  OSC.CTRL = OSC_RC32MEN_bm | OSC_PLLEN_bm | OSC_RC2MEN_bm; // Enable PLL

63 

64  while ( !(OSC.STATUS & OSC_PLLRDY_bm) )

65  ; // wait for PLL ready

66 

67  DFLLRC2M.CTRL = DFLL_ENABLE_bm;

68 

69  // use PLL as systemclk

70  CCP = CCP_IOREG_gc; /* allow changing CLK.CTRL */

71  CLK.CTRL = CLK_SCLKSEL_PLL_gc; // use PLL output as system clock

72 

73 }