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sysclk.h
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1 
43 /*
44  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45  */
46 #ifndef XMEGA_SYSCLK_H_INCLUDED
47 #define XMEGA_SYSCLK_H_INCLUDED
48 
49 #include <board_init.h>
50 #include <compiler.h>
51 #include <osc.h>
52 #include <pll.h>
53 #include "conf_clock.h"
54 
55 
56 
57 
58 /* Wrap old config into new one */
59 #ifdef CONFIG_OSC_AUTOCAL
60 # if CONFIG_OSC_AUTOCAL == OSC_ID_RC2MHZ
61 # define CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC CONFIG_OSC_AUTOCAL_REF_OSC
62 # elif CONFIG_OSC_AUTOCAL == OSC_ID_RC32MHZ
63 # define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC CONFIG_OSC_AUTOCAL_REF_OSC
64 # else
65 # error Bad configuration of CONFIG_OSC_AUTOCAL and/or CONFIG_OSC_AUTOCAL_REF_OSC
66 # endif
67 #endif
68 
69 // Use 2 MHz with no prescaling if config was empty.
70 #ifndef CONFIG_SYSCLK_SOURCE
71 # define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC2MHZ
72 #endif /* CONFIG_SYSCLK_SOURCE */
73 
74 #ifndef CONFIG_SYSCLK_PSADIV
75 # define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_1
76 #endif /* CONFIG_SYSCLK_PSADIV */
77 
78 #ifndef CONFIG_SYSCLK_PSBCDIV
79 # define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1
80 #endif /* CONFIG_SYSCLK_PSBCDIV */
81 
82 
84 
85 #define SYSCLK_SRC_RC2MHZ CLK_SCLKSEL_RC2M_gc
87 #define SYSCLK_SRC_RC32MHZ CLK_SCLKSEL_RC32M_gc
89 #define SYSCLK_SRC_RC32KHZ CLK_SCLKSEL_RC32K_gc
91 #define SYSCLK_SRC_XOSC CLK_SCLKSEL_XOSC_gc
93 #define SYSCLK_SRC_PLL CLK_SCLKSEL_PLL_gc
95 
96 
98 
99 #define SYSCLK_PSADIV_1 CLK_PSADIV_1_gc
100 #define SYSCLK_PSADIV_2 CLK_PSADIV_2_gc
101 #define SYSCLK_PSADIV_4 CLK_PSADIV_4_gc
102 #define SYSCLK_PSADIV_8 CLK_PSADIV_8_gc
103 #define SYSCLK_PSADIV_16 CLK_PSADIV_16_gc
104 #define SYSCLK_PSADIV_32 CLK_PSADIV_32_gc
105 #define SYSCLK_PSADIV_64 CLK_PSADIV_64_gc
106 #define SYSCLK_PSADIV_128 CLK_PSADIV_128_gc
107 #define SYSCLK_PSADIV_256 CLK_PSADIV_256_gc
108 #define SYSCLK_PSADIV_512 CLK_PSADIV_512_gc
109 
110 
111 
113 
114 #define SYSCLK_PSBCDIV_1_1 CLK_PSBCDIV_1_1_gc
116 #define SYSCLK_PSBCDIV_1_2 CLK_PSBCDIV_1_2_gc
118 #define SYSCLK_PSBCDIV_4_1 CLK_PSBCDIV_4_1_gc
120 #define SYSCLK_PSBCDIV_2_2 CLK_PSBCDIV_2_2_gc
122 
123 
125 enum sysclk_port_id {
126  SYSCLK_PORT_GEN,
127  SYSCLK_PORT_A,
128  SYSCLK_PORT_B,
129  SYSCLK_PORT_C,
130  SYSCLK_PORT_D,
131  SYSCLK_PORT_E,
132  SYSCLK_PORT_F,
133 };
134 
140 #define SYSCLK_DMA PR_DMA_bm
141 #define SYSCLK_EDMA PR_EDMA_bm
142 #define SYSCLK_EVSYS PR_EVSYS_bm
143 #define SYSCLK_RTC PR_RTC_bm
144 #define SYSCLK_EBI PR_EBI_bm
145 #define SYSCLK_AES PR_AES_bm
146 #define SYSCLK_USB PR_USB_bm
147 #define SYSCLK_XCL PR_XCL_bm
148 
149 
150 
155 #define SYSCLK_AC PR_AC_bm
156 #define SYSCLK_ADC PR_ADC_bm
157 #define SYSCLK_DAC PR_DAC_bm
158 
159 
160 
165 #define SYSCLK_TC0 PR_TC0_bm
166 #define SYSCLK_TC1 PR_TC1_bm
167 #define SYSCLK_TC4 PR_TC4_bm
168 #define SYSCLK_TC5 PR_TC5_bm
169 #define SYSCLK_HIRES PR_HIRES_bm
170 #define SYSCLK_SPI PR_SPI_bm
171 #define SYSCLK_USART0 PR_USART0_bm
172 #define SYSCLK_USART1 PR_USART1_bm
173 #define SYSCLK_TWI PR_TWI_bm
174 
175 
176 
183 #define SYSCLK_RTCSRC_ULP CLK_RTCSRC_ULP_gc
184 
185 #define SYSCLK_RTCSRC_TOSC CLK_RTCSRC_TOSC_gc
186 
187 #define SYSCLK_RTCSRC_RCOSC CLK_RTCSRC_RCOSC_gc
188 
189 #define SYSCLK_RTCSRC_TOSC32 CLK_RTCSRC_TOSC32_gc
190 
191 #define SYSCLK_RTCSRC_RCOSC32 CLK_RTCSRC_RCOSC32_gc
192 
193 #define SYSCLK_RTCSRC_EXTCLK CLK_RTCSRC_EXTCLK_gc
194 
197 #if XMEGA_AU || XMEGA_B || XMEGA_C
198 
200 #define USBCLK_SRC_RCOSC 0
202 #define USBCLK_SRC_PLL 1
204 
205 
217 #ifdef __DOXYGEN__
218 # define CONFIG_USBCLK_SOURCE
219 #endif
220 
221 #endif // XMEGA_AU || XMEGA_B || XMEGA_C
222 
223 #ifndef __ASSEMBLY__
224 
229 
241 static inline uint32_t sysclk_get_main_hz(void)
242 {
243  switch (CONFIG_SYSCLK_SOURCE) {
244  case SYSCLK_SRC_RC2MHZ:
245  return 2000000UL;
246  case SYSCLK_SRC_RC32MHZ:
247 #ifdef CONFIG_OSC_RC32_CAL
248  return CONFIG_OSC_RC32_CAL;
249 #else
250  return 32000000UL;
251 #endif
252 
253  case SYSCLK_SRC_RC32KHZ:
254  return 32768UL;
255 
256 #ifdef BOARD_XOSC_HZ
257  case SYSCLK_SRC_XOSC:
258  return BOARD_XOSC_HZ;
259 #endif
260 
261 #ifdef CONFIG_PLL0_SOURCE
262  case SYSCLK_SRC_PLL:
263  return pll_get_default_rate(0);
264 #endif
265 
266  default:
267  //unhandled_case(CONFIG_SYSCLK_SOURCE);
268  return 0;
269  }
270 }
271 
279 static inline uint32_t sysclk_get_per4_hz(void)
280 {
281  uint8_t shift = 0;
282 
283 #if XMEGA_E
284  if (CONFIG_SYSCLK_PSADIV > SYSCLK_PSADIV_512) {
285  switch (CONFIG_SYSCLK_PSADIV) {
286  case SYSCLK_PSADIV_6:
287  return sysclk_get_main_hz() / 6;
288  case SYSCLK_PSADIV_10:
289  return sysclk_get_main_hz() / 10;
290  case SYSCLK_PSADIV_12:
291  return sysclk_get_main_hz() / 12;
292  case SYSCLK_PSADIV_24:
293  return sysclk_get_main_hz() / 24;
294  case SYSCLK_PSADIV_48:
295  return sysclk_get_main_hz() / 48;
296  default:
297  //unhandled_case;
298  return 0;
299  }
300  }
301 #endif
302  if (CONFIG_SYSCLK_PSADIV & (1U << CLK_PSADIV_gp)) {
303  shift = (CONFIG_SYSCLK_PSADIV >> (1 + CLK_PSADIV_gp)) + 1;
304  }
305 
306  return sysclk_get_main_hz() >> shift;
307 }
308 
316 static inline uint32_t sysclk_get_per2_hz(void)
317 {
318  switch (CONFIG_SYSCLK_PSBCDIV) {
319  case SYSCLK_PSBCDIV_1_1: /* Fall through */
320  case SYSCLK_PSBCDIV_1_2:
321  return sysclk_get_per4_hz();
322 
323  case SYSCLK_PSBCDIV_4_1:
324  return sysclk_get_per4_hz() / 4;
325 
326  case SYSCLK_PSBCDIV_2_2:
327  return sysclk_get_per4_hz() / 2;
328 
329  default:
330  //unhandled_case(CONFIG_SYSCLK_PSBCDIV);
331  return 0;
332  }
333 }
334 
343 static inline uint32_t sysclk_get_per_hz(void)
344 {
345  if (CONFIG_SYSCLK_PSBCDIV & (1U << CLK_PSBCDIV_gp))
346  return sysclk_get_per2_hz() / 2;
347  else
348  return sysclk_get_per2_hz();
349 }
350 
356 static inline uint32_t sysclk_get_cpu_hz(void)
357 {
358  return sysclk_get_per_hz();
359 }
360 
369 static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
370 {
371  if (module == NULL) {
372  Assert(false);
373  return 0;
374  }
375 #ifdef AES
376  else if (module == &AES) {
377  return sysclk_get_per_hz();
378  }
379 #endif
380 #ifdef EBI
381  else if (module == &EBI) {
382  return sysclk_get_per2_hz();
383  }
384 #endif
385 #ifdef RTC
386  else if (module == &RTC) {
387  return sysclk_get_per_hz();
388  }
389 #endif
390 #ifdef EVSYS
391  else if (module == &EVSYS) {
392  return sysclk_get_per_hz();
393  }
394 #endif
395 #ifdef DMA
396  else if (module == &DMA) {
397  return sysclk_get_per_hz();
398  }
399 #endif
400 #ifdef EDMA
401  else if (module == &EDMA) {
402  return sysclk_get_per_hz();
403  }
404 #endif
405 #ifdef ACA
406  else if (module == &ACA) {
407  return sysclk_get_per_hz();
408  }
409 #endif
410 #ifdef ACB
411  else if (module == &ACB) {
412  return sysclk_get_per_hz();
413  }
414 #endif
415 #ifdef ADCA
416  else if (module == &ADCA) {
417  return sysclk_get_per_hz();
418  }
419 #endif
420 #ifdef ADCB
421  else if (module == &ADCB) {
422  return sysclk_get_per_hz();
423  }
424 #endif
425 #ifdef DACA
426  else if (module == &DACA) {
427  return sysclk_get_per_hz();
428  }
429 #endif
430 // Workaround for bad XMEGA D header file
431 #if !XMEGA_D
432 #ifdef DACB
433  else if (module == &DACB) {
434  return sysclk_get_per_hz();
435  }
436 #endif
437 #endif // Workaround end
438 #ifdef FAULTC0
439  else if (module == &FAULTC0) {
440  return sysclk_get_per_hz();
441  }
442 #endif
443 #ifdef FAULTC1
444  else if (module == &FAULTC1) {
445  return sysclk_get_per_hz();
446  }
447 #endif
448 #ifdef TCC0
449  else if (module == &TCC0) {
450  return sysclk_get_per_hz();
451  }
452 #endif
453 #ifdef TCD0
454  else if (module == &TCD0) {
455  return sysclk_get_per_hz();
456  }
457 #endif
458 #ifdef TCE0
459  else if (module == &TCE0) {
460  return sysclk_get_per_hz();
461  }
462 #endif
463 #ifdef TCF0
464  else if (module == &TCF0) {
465  return sysclk_get_per_hz();
466  }
467 #endif
468 #ifdef TCC1
469  else if (module == &TCC1) {
470  return sysclk_get_per_hz();
471  }
472 #endif
473 #ifdef TCD1
474  else if (module == &TCD1) {
475  return sysclk_get_per_hz();
476  }
477 #endif
478 #ifdef TCE1
479  else if (module == &TCE1) {
480  return sysclk_get_per_hz();
481  }
482 #endif
483 #ifdef TCF1
484  else if (module == &TCF1) {
485  return sysclk_get_per_hz();
486  }
487 #endif
488 #ifdef TCC4
489  else if (module == &TCC4) {
490  return sysclk_get_per_hz();
491  }
492 #endif
493 #ifdef TCC5
494  else if (module == &TCC5) {
495  return sysclk_get_per_hz();
496  }
497 #endif
498 #ifdef TCD4
499  else if (module == &TCD4) {
500  return sysclk_get_per_hz();
501  }
502 #endif
503 #ifdef TCD5
504  else if (module == &TCD5) {
505  return sysclk_get_per_hz();
506  }
507 #endif
508 #ifdef HIRESC
509  else if (module == &HIRESC) {
510  return sysclk_get_per4_hz();
511  }
512 #endif
513 #ifdef HIRESD
514  else if (module == &HIRESD) {
515  return sysclk_get_per4_hz();
516  }
517 #endif
518 #ifdef HIRESE
519  else if (module == &HIRESE) {
520  return sysclk_get_per4_hz();
521  }
522 #endif
523 #ifdef HIRESF
524  else if (module == &HIRESF) {
525  return sysclk_get_per4_hz();
526  }
527 #endif
528 #ifdef SPIC
529  else if (module == &SPIC) {
530  return sysclk_get_per_hz();
531  }
532 #endif
533 #ifdef SPID
534  else if (module == &SPID) {
535  return sysclk_get_per_hz();
536  }
537 #endif
538 #ifdef SPIE
539  else if (module == &SPIE) {
540  return sysclk_get_per_hz();
541  }
542 #endif
543 #ifdef SPIF
544  else if (module == &SPIF) {
545  return sysclk_get_per_hz();
546  }
547 #endif
548 #ifdef USARTC0
549  else if (module == &USARTC0) {
550  return sysclk_get_per_hz();
551  }
552 #endif
553 #ifdef USARTD0
554  else if (module == &USARTD0) {
555  return sysclk_get_per_hz();
556  }
557 #endif
558 #ifdef USARTE0
559  else if (module == &USARTE0) {
560  return sysclk_get_per_hz();
561  }
562 #endif
563 #ifdef USARTF0
564  else if (module == &USARTF0) {
565  return sysclk_get_per_hz();
566  }
567 #endif
568 #ifdef USARTC1
569  else if (module == &USARTC1) {
570  return sysclk_get_per_hz();
571  }
572 #endif
573 #ifdef USARTD1
574  else if (module == &USARTD1) {
575  return sysclk_get_per_hz();
576  }
577 #endif
578 #ifdef USARTE1
579  else if (module == &USARTE1) {
580  return sysclk_get_per_hz();
581  }
582 #endif
583 #ifdef USARTF1
584  else if (module == &USARTF1) {
585  return sysclk_get_per_hz();
586  }
587 #endif
588 #ifdef TWIC
589  else if (module == &TWIC) {
590  return sysclk_get_per_hz();
591  }
592 #endif
593 #ifdef TWID
594  else if (module == &TWID) {
595  return sysclk_get_per_hz();
596  }
597 #endif
598 #ifdef TWIE
599  else if (module == &TWIE) {
600  return sysclk_get_per_hz();
601  }
602 #endif
603 #ifdef TWIF
604  else if (module == &TWIF) {
605  return sysclk_get_per_hz();
606  }
607 #endif
608 #ifdef XCL
609  else if (module == &XCL) {
610  return sysclk_get_per_hz();
611  }
612 #endif
613  else {
614  Assert(false);
615  return 0;
616  }
617 }
618 
620 
622 
623 
631 extern void sysclk_enable_module(enum sysclk_port_id port, uint8_t id);
632 
640 extern void sysclk_disable_module(enum sysclk_port_id port, uint8_t id);
641 
650 static inline void sysclk_enable_peripheral_clock(const volatile void *module)
651 {
652  if (module == NULL) {
653  Assert(false);
654  }
655 #ifdef AES
656  else if (module == &AES) {
657  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_AES);
658  }
659 #endif
660 #ifdef EBI
661  else if (module == &EBI) {
662  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EBI);
663  }
664 #endif
665 #ifdef RTC
666  else if (module == &RTC) {
667  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_RTC);
668  }
669 #endif
670 #ifdef EVSYS
671  else if (module == &EVSYS) {
672  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
673  }
674 #endif
675 #ifdef DMA
676  else if (module == &DMA) {
677  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_DMA);
678  }
679 #endif
680 #ifdef EDMA
681  else if (module == &EDMA) {
682  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EDMA);
683  }
684 #endif
685 #ifdef ACA
686  else if (module == &ACA) {
687  sysclk_enable_module(SYSCLK_PORT_A, SYSCLK_AC);
688  }
689 #endif
690 #ifdef ACB
691  else if (module == &ACB) {
692  sysclk_enable_module(SYSCLK_PORT_B, SYSCLK_AC);
693  }
694 #endif
695 #ifdef ADCA
696  else if (module == &ADCA) {
697  sysclk_enable_module(SYSCLK_PORT_A, SYSCLK_ADC);
698  }
699 #endif
700 #ifdef ADCB
701  else if (module == &ADCB) {
702  sysclk_enable_module(SYSCLK_PORT_B, SYSCLK_ADC);
703  }
704 #endif
705 #ifdef DACA
706  else if (module == &DACA) {
707  sysclk_enable_module(SYSCLK_PORT_A, SYSCLK_DAC);
708  }
709 #endif
710 // Workaround for bad XMEGA D header file
711 #if !XMEGA_D
712 #ifdef DACB
713  else if (module == &DACB) {
714  sysclk_enable_module(SYSCLK_PORT_B, SYSCLK_DAC);
715  }
716 #endif
717 #endif // Workaround end
718 #ifdef TCC0
719  else if (module == &TCC0) {
720  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC0);
721  }
722 #endif
723 #ifdef TCD0
724  else if (module == &TCD0) {
725  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_TC0);
726  }
727 #endif
728 #ifdef TCE0
729  else if (module == &TCE0) {
730  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_TC0);
731  }
732 #endif
733 #ifdef TCF0
734  else if (module == &TCF0) {
735  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_TC0);
736  }
737 #endif
738 #ifdef TCC1
739  else if (module == &TCC1) {
740  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC1);
741  }
742 #endif
743 #ifdef TCD1
744  else if (module == &TCD1) {
745  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_TC1);
746  }
747 #endif
748 #ifdef TCE1
749  else if (module == &TCE1) {
750  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_TC1);
751  }
752 #endif
753 #ifdef TCF1
754  else if (module == &TCF1) {
755  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_TC1);
756  }
757 #endif
758 #ifdef TCC4
759  else if (module == &TCC4) {
760  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC4);
761  }
762 #endif
763 #ifdef TCC5
764  else if (module == &TCC5) {
765  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC5);
766  }
767 #endif
768 #ifdef TCD4
769  else if (module == &TCD4) {
770  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_TC4);
771  }
772 #endif
773 #ifdef TCD5
774  else if (module == &TCD5) {
775  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_TC5);
776  }
777 #endif
778 #ifdef HIRESC
779  else if (module == &HIRESC) {
780  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_HIRES);
781  }
782 #endif
783 #ifdef HIRESD
784  else if (module == &HIRESD) {
785  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_HIRES);
786  }
787 #endif
788 #ifdef HIRESE
789  else if (module == &HIRESE) {
790  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_HIRES);
791  }
792 #endif
793 #ifdef HIRESF
794  else if (module == &HIRESF) {
795  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_HIRES);
796  }
797 #endif
798 #ifdef SPIC
799  else if (module == &SPIC) {
800  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_SPI);
801  }
802 #endif
803 #ifdef SPID
804  else if (module == &SPID) {
805  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_SPI);
806  }
807 #endif
808 #ifdef SPIE
809  else if (module == &SPIE) {
810  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_SPI);
811  }
812 #endif
813 #ifdef SPIF
814  else if (module == &SPIF) {
815  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_SPI);
816  }
817 #endif
818 #ifdef USARTC0
819  else if (module == &USARTC0) {
820  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_USART0);
821  }
822 #endif
823 #ifdef USARTD0
824  else if (module == &USARTD0) {
825  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_USART0);
826  }
827 #endif
828 #ifdef USARTE0
829  else if (module == &USARTE0) {
830  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_USART0);
831  }
832 #endif
833 #ifdef USARTF0
834  else if (module == &USARTF0) {
835  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_USART0);
836  }
837 #endif
838 #ifdef USARTC1
839  else if (module == &USARTC1) {
840  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_USART1);
841  }
842 #endif
843 #ifdef USARTD1
844  else if (module == &USARTD1) {
845  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_USART1);
846  }
847 #endif
848 #ifdef USARTE1
849  else if (module == &USARTE1) {
850  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_USART1);
851  }
852 #endif
853 #ifdef USARTF1
854  else if (module == &USARTF1) {
855  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_USART1);
856  }
857 #endif
858 #ifdef TWIC
859  else if (module == &TWIC) {
860  sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TWI);
861  }
862 #endif
863 #ifdef TWID
864  else if (module == &TWID) {
865  sysclk_enable_module(SYSCLK_PORT_D, SYSCLK_TWI);
866  }
867 #endif
868 #ifdef TWIE
869  else if (module == &TWIE) {
870  sysclk_enable_module(SYSCLK_PORT_E, SYSCLK_TWI);
871  }
872 #endif
873 #ifdef TWIF
874  else if (module == &TWIF) {
875  sysclk_enable_module(SYSCLK_PORT_F, SYSCLK_TWI);
876  }
877 #endif
878 #ifdef XCL
879  else if (module == &XCL) {
880  sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_XCL);
881  }
882 #endif
883  else {
884  Assert(false);
885  }
886 }
887 
896 static inline void sysclk_disable_peripheral_clock(const volatile void *module)
897 {
898  if (module == NULL) {
899  Assert(false);
900  }
901 #ifdef AES
902  else if (module == &AES) {
903  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_AES);
904  }
905 #endif
906 #ifdef EBI
907  else if (module == &EBI) {
908  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_EBI);
909  }
910 #endif
911 #ifdef RTC
912  else if (module == &RTC) {
913  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_RTC);
914  }
915 #endif
916 #ifdef EVSYS
917  else if (module == &EVSYS) {
918  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
919  }
920 #endif
921 #ifdef DMA
922  else if (module == &DMA) {
923  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_DMA);
924  }
925 #endif
926 #ifdef EDMA
927  else if (module == &EDMA) {
928  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_EDMA);
929  }
930 #endif
931 #ifdef ACA
932  else if (module == &ACA) {
933  sysclk_disable_module(SYSCLK_PORT_A, SYSCLK_AC);
934  }
935 #endif
936 #ifdef ACB
937  else if (module == &ACB) {
938  sysclk_disable_module(SYSCLK_PORT_B, SYSCLK_AC);
939  }
940 #endif
941 #ifdef ADCA
942  else if (module == &ADCA) {
943  sysclk_disable_module(SYSCLK_PORT_A, SYSCLK_ADC);
944  }
945 #endif
946 #ifdef ADCB
947  else if (module == &ADCB) {
948  sysclk_disable_module(SYSCLK_PORT_B, SYSCLK_ADC);
949  }
950 #endif
951 #ifdef DACA
952  else if (module == &DACA) {
953  sysclk_disable_module(SYSCLK_PORT_A, SYSCLK_DAC);
954  }
955 #endif
956 // Workaround for bad XMEGA D header file
957 #if !XMEGA_D
958 #ifdef DACB
959  else if (module == &DACB) {
960  sysclk_disable_module(SYSCLK_PORT_B, SYSCLK_DAC);
961  }
962 #endif
963 #endif // Workaround end
964 #ifdef TCC0
965  else if (module == &TCC0) {
966  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_TC0);
967  }
968 #endif
969 #ifdef TCD0
970  else if (module == &TCD0) {
971  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_TC0);
972  }
973 #endif
974 #ifdef TCE0
975  else if (module == &TCE0) {
976  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_TC0);
977  }
978 #endif
979 #ifdef TCF0
980  else if (module == &TCF0) {
981  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_TC0);
982  }
983 #endif
984 #ifdef TCC1
985  else if (module == &TCC1) {
986  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_TC1);
987  }
988 #endif
989 #ifdef TCD1
990  else if (module == &TCD1) {
991  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_TC1);
992  }
993 #endif
994 #ifdef TCE1
995  else if (module == &TCE1) {
996  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_TC1);
997  }
998 #endif
999 #ifdef TCF1
1000  else if (module == &TCF1) {
1001  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_TC1);
1002  }
1003 #endif
1004 #ifdef TCC4
1005  else if (module == &TCC4) {
1006  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_TC4);
1007  }
1008 #endif
1009 #ifdef TCC5
1010  else if (module == &TCC5) {
1011  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_TC5);
1012  }
1013 #endif
1014 #ifdef TCD4
1015  else if (module == &TCD4) {
1016  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_TC4);
1017  }
1018 #endif
1019 #ifdef TCD5
1020  else if (module == &TCD5) {
1021  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_TC5);
1022  }
1023 #endif
1024 #ifdef HIRESC
1025  else if (module == &HIRESC) {
1026  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_HIRES);
1027  }
1028 #endif
1029 #ifdef HIRESD
1030  else if (module == &HIRESD) {
1031  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_HIRES);
1032  }
1033 #endif
1034 #ifdef HIRESE
1035  else if (module == &HIRESE) {
1036  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_HIRES);
1037  }
1038 #endif
1039 #ifdef HIRESF
1040  else if (module == &HIRESF) {
1041  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_HIRES);
1042  }
1043 #endif
1044 #ifdef SPIC
1045  else if (module == &SPIC) {
1046  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_SPI);
1047  }
1048 #endif
1049 #ifdef SPID
1050  else if (module == &SPID) {
1051  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_SPI);
1052  }
1053 #endif
1054 #ifdef SPIE
1055  else if (module == &SPIE) {
1056  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_SPI);
1057  }
1058 #endif
1059 #ifdef SPIF
1060  else if (module == &SPIF) {
1061  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_SPI);
1062  }
1063 #endif
1064 #ifdef USARTC0
1065  else if (module == &USARTC0) {
1066  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_USART0);
1067  }
1068 #endif
1069 #ifdef USARTD0
1070  else if (module == &USARTD0) {
1071  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_USART0);
1072  }
1073 #endif
1074 #ifdef USARTE0
1075  else if (module == &USARTE0) {
1076  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_USART0);
1077  }
1078 #endif
1079 #ifdef USARTF0
1080  else if (module == &USARTF0) {
1081  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_USART0);
1082  }
1083 #endif
1084 #ifdef USARTC1
1085  else if (module == &USARTC1) {
1086  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_USART1);
1087  }
1088 #endif
1089 #ifdef USARTD1
1090  else if (module == &USARTD1) {
1091  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_USART1);
1092  }
1093 #endif
1094 #ifdef USARTE1
1095  else if (module == &USARTE1) {
1096  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_USART1);
1097  }
1098 #endif
1099 #ifdef USARTF1
1100  else if (module == &USARTF1) {
1101  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_USART1);
1102  }
1103 #endif
1104 #ifdef TWIC
1105  else if (module == &TWIC) {
1106  sysclk_disable_module(SYSCLK_PORT_C, SYSCLK_TWI);
1107  }
1108 #endif
1109 #ifdef TWID
1110  else if (module == &TWID) {
1111  sysclk_disable_module(SYSCLK_PORT_D, SYSCLK_TWI);
1112  }
1113 #endif
1114 #ifdef TWIE
1115  else if (module == &TWIE) {
1116  sysclk_disable_module(SYSCLK_PORT_E, SYSCLK_TWI);
1117  }
1118 #endif
1119 #ifdef TWIF
1120  else if (module == &TWIF) {
1121  sysclk_disable_module(SYSCLK_PORT_F, SYSCLK_TWI);
1122  }
1123 #endif
1124 #ifdef XCL
1125  else if (module == &XCL) {
1126  sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_XCL);
1127  }
1128 #endif
1129  else {
1130  Assert(false);
1131  }
1132 }
1133 
1145 static inline bool sysclk_module_is_enabled(enum sysclk_port_id port,
1146  uint8_t id)
1147 {
1148  uint8_t mask = *((uint8_t *)&PR.PRGEN + port);
1149  return (mask & id) == 0;
1150 }
1151 
1152 #if XMEGA_AU || XMEGA_B || XMEGA_C || defined(__DOXYGEN__)
1153 # if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
1154 # if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_RCOSC)
1155 # define USBCLK_STARTUP_TIMEOUT 1
1156 # elif (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL)
1157 # if (CONFIG_PLL0_SOURCE == PLL_SRC_XOSC)
1158 # define USBCLK_STARTUP_TIMEOUT XOSC_STARTUP_TIMEOUT
1159 # elif (CONFIG_PLL0_SOURCE == PLL_SRC_RC32MHZ)
1160 # define USBCLK_STARTUP_TIMEOUT 1
1161 # elif (CONFIG_PLL0_SOURCE == PLL_SRC_RC2MHZ)
1162 # define USBCLK_STARTUP_TIMEOUT 1
1163 # else
1164 # error Unknow value for CONFIG_PLL0_SOURCE, see conf_clock.h.
1165 # endif
1166 # endif
1167 # else /* CONFIG_USBCLK_SOURCE not defined */
1168 # define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC
1169 # define USBCLK_STARTUP_TIMEOUT 1
1170 # endif /* CONFIG_USBCLK_SOURCE */
1171 void sysclk_enable_usb(uint8_t frequency);
1172 void sysclk_disable_usb(void);
1173 #endif /* XMEGA_AU || XMEGA_B || XMEGA_C */
1174 
1175 
1177 
1178 
1192 static inline void sysclk_set_prescalers(uint8_t psadiv, uint8_t psbcdiv)
1193 {
1194  CCP = CCP_IOREG_gc;
1195  CLK.PSCTRL = (psadiv | psbcdiv);
1196 }
1197 
1204 static inline void sysclk_set_source(uint8_t src)
1205 {
1206  CCP = CCP_IOREG_gc;
1207  CLK.CTRL = src;
1208 }
1209 
1216 static inline void sysclk_lock(void)
1217 {
1218  CCP = CCP_IOREG_gc;
1219  CLK.LOCK = CLK_LOCK_bm;
1220 }
1221 
1223 
1236 static inline void sysclk_rtcsrc_enable(uint8_t id)
1237 {
1238  Assert((id & ~CLK_RTCSRC_gm) == 0);
1239 
1240  switch (id) {
1241  case SYSCLK_RTCSRC_RCOSC:
1242 #if !XMEGA_A && !XMEGA_D
1243  case SYSCLK_RTCSRC_RCOSC32:
1244 #endif
1245  osc_enable(OSC_ID_RC32KHZ);
1246  osc_wait_ready(OSC_ID_RC32KHZ);
1247  break;
1248  case SYSCLK_RTCSRC_TOSC:
1249  case SYSCLK_RTCSRC_TOSC32:
1250 #if !XMEGA_A && !XMEGA_D
1251  case SYSCLK_RTCSRC_EXTCLK:
1252 #endif
1253  osc_enable(OSC_ID_XOSC);
1254  osc_wait_ready(OSC_ID_XOSC);
1255  break;
1256  }
1257 
1258  CLK.RTCCTRL = id | CLK_RTCEN_bm;
1259 }
1260 
1264 static inline void sysclk_rtcsrc_disable(void)
1265 {
1266  CLK.RTCCTRL = 0;
1267 }
1268 
1271 
1273 
1274 extern void sysclk_init(void);
1275 
1277 
1278 #endif /* !__ASSEMBLY__ */
1279 
1281 
1282 #endif /* XMEGA_SYSCLK_H_INCLUDED */
SYSCLK_TC4
#define SYSCLK_TC4
Timer/Counter 0.
Definition: sysclk.h:167
SYSCLK_AC
#define SYSCLK_AC
Analog Comparator.
Definition: sysclk.h:155
sysclk_get_cpu_hz
static uint32_t sysclk_get_cpu_hz(void)
Return the current rate in Hz of the CPU clock.
Definition: sysclk.h:356
SYSCLK_RTC
#define SYSCLK_RTC
Real-Time Counter.
Definition: sysclk.h:143
SYSCLK_EDMA
#define SYSCLK_EDMA
EDMA Controller.
Definition: sysclk.h:141
sysclk_lock
static void sysclk_lock(void)
Lock the system clock configuration.
Definition: sysclk.h:1216
SYSCLK_SRC_XOSC
#define SYSCLK_SRC_XOSC
External oscillator.
Definition: sysclk.h:92
board_init.h
Standard board header file. Diese Datei enthält die Standardparameter und Pinbelegungen für das BMS B...
SYSCLK_USART0
#define SYSCLK_USART0
USART 0.
Definition: sysclk.h:171
SYSCLK_RTCSRC_RCOSC32
#define SYSCLK_RTCSRC_RCOSC32
Definition: sysclk.h:191
SYSCLK_TC5
#define SYSCLK_TC5
Timer/Counter 1.
Definition: sysclk.h:168
SYSCLK_EBI
#define SYSCLK_EBI
Ext Bus Interface.
Definition: sysclk.h:144
compiler.h
Commonly used includes, types and macros.
Assert
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:46
SYSCLK_USART1
#define SYSCLK_USART1
USART 1.
Definition: sysclk.h:172
sysclk_rtcsrc_disable
static void sysclk_rtcsrc_disable(void)
Disable RTC clock.
Definition: sysclk.h:1264
sysclk_set_source
static void sysclk_set_source(uint8_t src)
Change the source of the main system clock.
Definition: sysclk.h:1204
SYSCLK_TC1
#define SYSCLK_TC1
Timer/Counter 1.
Definition: sysclk.h:166
sysclk_get_peripheral_bus_hz
static uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
Retrieves the current rate in Hz of the Peripheral Bus clock attached to the specified peripheral...
Definition: sysclk.h:369
sysclk_enable_module
void sysclk_enable_module(enum sysclk_port_id port, uint8_t id)
Enable the clock to peripheral id on port port.
Definition: sysclk.c:176
SYSCLK_PSBCDIV_4_1
#define SYSCLK_PSBCDIV_4_1
Prescale CLKper2, CLKper and CLKcpu by 4.
Definition: sysclk.h:119
SYSCLK_PORT_B
Devices on PORTB.
Definition: sysclk.h:128
SYSCLK_DAC
#define SYSCLK_DAC
D/A Converter.
Definition: sysclk.h:157
SYSCLK_DMA
#define SYSCLK_DMA
DMA Controller.
Definition: sysclk.h:140
pll.h
Chip-specific PLL management functions.
SYSCLK_EVSYS
#define SYSCLK_EVSYS
Event System.
Definition: sysclk.h:142
sysclk_port_id
sysclk_port_id
Definition: sysclk.h:125
SYSCLK_XCL
#define SYSCLK_XCL
USB Module.
Definition: sysclk.h:147
OSC_ID_XOSC
#define OSC_ID_XOSC
External Oscillator.
Definition: osc.h:70
sysclk_enable_peripheral_clock
static void sysclk_enable_peripheral_clock(const volatile void *module)
Enable a peripheral&#39;s clock from its base address.
Definition: sysclk.h:650
SYSCLK_TC0
#define SYSCLK_TC0
Timer/Counter 0.
Definition: sysclk.h:165
sysclk_rtcsrc_enable
static void sysclk_rtcsrc_enable(uint8_t id)
Enable RTC clock with specified clock source.
Definition: sysclk.h:1236
sysclk_get_per2_hz
static uint32_t sysclk_get_per2_hz(void)
Return the current rate in Hz of clk_PER2.
Definition: sysclk.h:316
SYSCLK_ADC
#define SYSCLK_ADC
A/D Converter.
Definition: sysclk.h:156
SYSCLK_SPI
#define SYSCLK_SPI
SPI controller.
Definition: sysclk.h:170
SYSCLK_SRC_RC32KHZ
#define SYSCLK_SRC_RC32KHZ
Internal 32 KHz RC oscillator.
Definition: sysclk.h:90
osc.h
Chip-specific oscillator management functions.
SYSCLK_TWI
#define SYSCLK_TWI
TWI controller.
Definition: sysclk.h:173
sysclk_get_per4_hz
static uint32_t sysclk_get_per4_hz(void)
Return the current rate in Hz of clk_PER4.
Definition: sysclk.h:279
SYSCLK_PORT_A
Devices on PORTA.
Definition: sysclk.h:127
SYSCLK_PSBCDIV_1_2
#define SYSCLK_PSBCDIV_1_2
Prescale CLKper and CLKcpu by 2.
Definition: sysclk.h:117
sysclk_get_per_hz
static uint32_t sysclk_get_per_hz(void)
Return the current rate in Hz of clk_PER.
Definition: sysclk.h:343
SYSCLK_RTCSRC_RCOSC
#define SYSCLK_RTCSRC_RCOSC
Definition: sysclk.h:187
sysclk_get_main_hz
static uint32_t sysclk_get_main_hz(void)
Return the current rate in Hz of the main system clock.
Definition: sysclk.h:241
OSC_ID_RC32KHZ
#define OSC_ID_RC32KHZ
32 KHz Internal RC Oscillator
Definition: osc.h:68
SYSCLK_AES
#define SYSCLK_AES
AES Module.
Definition: sysclk.h:145
SYSCLK_PORT_GEN
Devices not associated with a specific port.
Definition: sysclk.h:126
SYSCLK_HIRES
#define SYSCLK_HIRES
Hi-Res Extension.
Definition: sysclk.h:169
SYSCLK_RTCSRC_TOSC32
#define SYSCLK_RTCSRC_TOSC32
Definition: sysclk.h:189
SYSCLK_PORT_D
Devices on PORTD.
Definition: sysclk.h:130
SYSCLK_PORT_E
Devices on PORTE.
Definition: sysclk.h:131
SYSCLK_PSADIV_512
#define SYSCLK_PSADIV_512
Prescale CLKper4 by 512.
Definition: sysclk.h:108
SYSCLK_PORT_C
Devices on PORTC.
Definition: sysclk.h:129
SYSCLK_SRC_RC2MHZ
#define SYSCLK_SRC_RC2MHZ
Internal 2 MHz RC oscillator.
Definition: sysclk.h:86
SYSCLK_PSBCDIV_1_1
#define SYSCLK_PSBCDIV_1_1
Do not prescale.
Definition: sysclk.h:115
sysclk_disable_peripheral_clock
static void sysclk_disable_peripheral_clock(const volatile void *module)
Disable a peripheral&#39;s clock from its base address.
Definition: sysclk.h:896
SYSCLK_SRC_RC32MHZ
#define SYSCLK_SRC_RC32MHZ
Internal 32 MHz RC oscillator.
Definition: sysclk.h:88
SYSCLK_PSBCDIV_2_2
#define SYSCLK_PSBCDIV_2_2
Prescale CLKper2 by 2, CLKper and CLKcpu by 4.
Definition: sysclk.h:121
SYSCLK_SRC_PLL
#define SYSCLK_SRC_PLL
Phase-Locked Loop.
Definition: sysclk.h:94
SYSCLK_RTCSRC_EXTCLK
#define SYSCLK_RTCSRC_EXTCLK
Definition: sysclk.h:193
SYSCLK_PORT_F
Devices on PORTF.
Definition: sysclk.h:132
sysclk_disable_module
void sysclk_disable_module(enum sysclk_port_id port, uint8_t id)
Disable the clock to peripheral id on port port.
Definition: sysclk.c:185
conf_clock.h
Chip-specific system clock manager configuration.
SYSCLK_RTCSRC_TOSC
#define SYSCLK_RTCSRC_TOSC
Definition: sysclk.h:185
sysclk_module_is_enabled
static bool sysclk_module_is_enabled(enum sysclk_port_id port, uint8_t id)
Check if the synchronous clock is enabled for a module.
Definition: sysclk.h:1145
sysclk_set_prescalers
static void sysclk_set_prescalers(uint8_t psadiv, uint8_t psbcdiv)
Set system clock prescaler configuration.
Definition: sysclk.h:1192
by Hanna